The use of TiSi.sub.2 to increase the conductivity of silicon and polycrystalline silicon areas is well known in the art. Field effect transistor 10 in FIG. 1 includes TiSi.sub.2 layers 6, 7, and 8 which increase the conductivity of gate 4, source 2, and drain 3, respectively. TiSi.sub.2 layers 6, 7, and 8 are formed using the direct reaction process. This process involves depositing a layer of titanium on the surace of transistor 10 and baking transistor 10 to cause the titanium layer to react with the silicon and polysilicon areas which are in contact with the titanium layer. The unreacted titanium is then removed.
The simple direct reaction process has critical limitations when used to form TiSi.sub.2 layers in both a polysilicon layer and doped areas in a substrate when used in the fabrication of very large scale integrated circuits. In very large scale integrated circuits, doped regions generally have a depth of approximately 0.2 microns. Thus the titanium layer deposited on the surface of the integrated circuit must be limited to about 0.1 microns because the reacting titanium will diffuse into the doped region and 0.1 microns of titanium will produce a layer of TiSi.sub.2 approximately 0.15 microns deep. If a thicker layer of titanium is used, the titanium disilicide layer may diffuse through (punch-through) the doped region to the substrate and thus cause excessive leakage current from the doped region to the substrate. However, to provide a TiSi.sub.2 layer which reduces the sheet resistance of the polycrystalline silicon layer to a minimum (i.e. less than 1 ohm/sq.), a TiSi.sub.2 layer of at least 0.15 microns of titanium is necessary. Thus using the prior art direct reaction method, the polycrystalline silicon regions cannot be provided with a TiSi.sub.2 layer which minimizes the sheet resistance of the polycrystalline silicon layer in very large scale integrated circuits.